LCD driver for layout and power savings

ABSTRACT

A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2. A plurality of blocking transistors can positioned between the input and selected digital signal lines, with at least one of the digital signal lines being coupled to a gate of each of the blocking transistors for controlling each of the blocking transistors. A level-shifter can also be positioned between selected active regions for one or more digital signal line.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to liquid crystal display(LCD) drivers, and more particularly, to digital signal control circuitsand methods for conserving power and minimizing layout space for usewith LCD drivers.

[0003] 2. Background Art

[0004] LCD displays are commonly used for applications such as computerdisplay monitors, television monitors, and other devices for displayingtext, photo, video, or other types of information. LCD displays may bemade of certain types of liquid crystal display material, as is wellunderstood by those familiar with display technologies. In typical LCDs,liquid crystal material fills the space or gap between a pair of row andcolumn substrates to form a cell or pixel. Perpendicular row and columnelectrodes are patterned on to the respective substrates to permit anelectric potential to be selectively created at particular points (i.e.,cells) on the display to alter the appearance of the liquid crystalmaterial. Row and column (data) drivers are utilized to address selectedcells.

[0005] Each of these LCD (row and column) drivers receive an n-bitdigital input data that is used to select one out of 2^(n) voltagelevels to be provided to the desired row or column electrodes. FIG. 1illustrates a conventional LCD driver circuit where n is equal to 2. The2-bit input data is processed by a 2×4 decoder for selecting one of thefour digital lines {D00, D01, D10, D11} to pass one of the four voltagelevels {V0, V1, V2, V3} to an output circuit and then on to the desiredelectrode. An optional sample and hold circuit designated S&H isprovided at the output for boosting the signal strength of the outputanalog voltage.

[0006]FIG. 2 illustrates a known signal-line routing scheme based on theconventional LCD driver in FIG. 1. The four voltage lines carrying thevoltage levels {V0, V1, V2, V3} are M2 (metal-2) lines, and the fourdecoded lines for carrying the decoded digital signals are M1 (metal-1)lines. The M2 and M1 lines are arranged perpendicular to each other. Theoutput is used for driving one column of the LCD cells. The M2 linesthat carry the analog voltages {V0, V1, V2, V3} extend further from whatis illustrated in FIG. 2, and are used to drive other columns of LCDcells via other decoders.

[0007]FIG. 3 illustrates the LCD driver circuit and routing scheme thatis similar to a commercial LCD driver distributed by NEC Corp., andknown as the “NEC uPD16632”. For simplicity, only n=2 bits are shown inFIG. 3 to select one of four voltage levels for output driving. Thereare 2n (i.e., 4) digital signal lines {a, a-bar, b, b-bar} that are usedfor controlling a matrix of 2n×2^(n) (i.e., 16) pass transistors, forselecting one of 2^(n) (i.e., 4) voltage levels as the output voltage.As compared with FIGS. 1 and 2, no decoder is used to process thedigital input data. The voltage levels {V0, V1, V2, V3} are carried bymetal lines that are fabricated by a metal-1 or metal-2 layer. The 2ndigital signal lines are carried by polysilicon lines that areperpendicular to the metal lines. Due to the column pitch andmetal/polysilicon line pitch considerations, even though the number ofpass transistors {M00, M01, . . . , M33} used is significantly higherthan illustrated in FIGS. 1 and 2, the actual layout is not necessarilylarger, and can actually be smaller, than the layout in FIGS. 1 and 2.

[0008] The pass transistors in FIG. 3 that have been circled (i.e., M00,M02, M10, M13, M21, M22, M31, M33} are depletion implanted to a negativethreshold voltage so that they are always turned “ON” regardless of thevoltage level (i.e., high or low) of each digital signal line {a, a-bar,b, b-bar}. In other words, these depletion implanted transistors operateas “don't care” transistors that pass whatever voltages are transmittedtherethrough. The negative threshold voltage of these depletionimplanted pass transistors enables the use of polysilicon lines as boththe digital signal lines and the gates of those pass transistors toachieve savings in layout. This will become apparent by viewing thelayout shown in FIG. 4.

[0009]FIG. 4 is a top view of a layout that is similar to the layout ofthe NEC uPD16632 of FIG. 3. In this example, n=3 bits are used. As aresult, there are 2n (i.e., 6) digital signal lines {a, a-bar, b, b-bar,c, c-bar}, and 2^(n) (i.e., 8) voltage levels {V0, V1, V2, V3, V4, V5,V6, V7}. These eight voltage levels are carried by eight active regionslabeled AR that include diffusion regions (e.g., n+ implanted). As knownin the art, a diffusion region is an n+ or p+ implanted and laterdiffused region (due to thermal cycles) in an active region surroundedby field oxide isolation. These eight voltage levels {V0, V1, V2, V3,V4, V5, V6, V7} are divided into even-numbered voltage levels {V0, V2,V4, V6} at one side of the layout of FIG. 4, and odd-numbered voltagelevels {V1, V3, V5, V7} at another side of the layout of FIG. 4. A DACoutput node is coupled to the action regions AR through metal-1 linesand metal-to-diffusion contacts. The six digital signal lines {a, a-bar,b, b-bar, c, c-bar} are carried by polysilicon lines, with six digitalsignal lines {a, a-bar, b, b-bar, c, c-bar} on a different side of thelayout. A pass transistor PT is formed where each polysilicon line {a,a-bar, b, b-bar, c, c-bar} crosses an active region AR, with the portionof the polysilicon overlapping the active region AR as the gate for thepass transistor. Again, each circled pass transistor is depletionimplanted through the use of a mask.

[0010] As shown in FIG. 4, the voltage levels {V0, V1, V2, V3, V4, V5,V6, V7} increase monotonously from V0 through V7. For example, V0 willbe selected as the output voltage if {a}, {b} and {c} are all digital“low” (i.e., 0). This is because the {a}, {b} and {c} lines overlapdepletion implanted transistors at the voltage level for V0 (i.e., thevoltage V0 passes through), and the {a-bar}, {b-bar} and {c-bar} lineswill carry a “high” signal (i.e., a=0, b=0, c=0) to pass the voltagelevel V0 to the DAC output. As a further example, V1 will be selected asthe output voltage if {a} and {b} are all digital “low” (i.e., 0), and{c} is digital “high”. This is because the {a}, {b} and {c-bar} linesoverlap depletion implanted transistors at the voltage level for V1(i.e., the voltage V1 passes through), and the {a-bar}, {b-bar} and {c}lines will carry a “high” signal (i.e., a=0, b=0, c=1) to pass thevoltage level V1 to the DAC output. As yet another example, V6 will beselected as the output voltage if {c} is digital “low” (i.e., 0), and{a} and {b} are both digital “high”. This is because the {a-bar},{b-bar} and {c} lines overlap depletion implanted transistors at thevoltage level for V6 (i.e., the voltage V6 passes through), and the {a},{b} and {c-bar} lines will carry a “high” signal (i.e., a=1, b=1, c=0)to pass the voltage level V6 to the DAC output. Using the samemethodology, and given the layout illustrated in FIG. 4, thecorresponding digital signals and selected voltage levels are asfollows: a b c Voltage Level Selected 0 0 0 V0 0 0 1 V1 0 1 0 V2 0 1 1V3 1 0 0 V4 1 0 1 V5 1 1 0 V6 1 1 1 V7

[0011] Unfortunately, the layouts in FIGS. 3 and 4 suffer from thedrawbacks that they take up much space, and require a large amount ofpower for driving the circuit.

SUMMARY OF THF INVENTION

[0012] It is an object of the present invention to provide an improveddigital signal control circuit that conserves power.

[0013] It is another object of the present invention to provide animproved digital signal control circuit that conserves layout space.

[0014] It is a further object of the present invention to provide animproved digital signal control circuit that has fewer or reduced signallines.

[0015] Improvements are needed to reduce the number of poly lines andpass transistors to save both layout space and power. As the gate ofeach pass transistor becomes a load for the {a, a-bar, b, b-bar, c,c-bar} signal driving lines, reduction of the poly lines and pass gateswill reduce power consumption.

[0016] In accordance with the foregoing and other objectives of theinvention, the present invention provides a driver circuit for use indriving displays, the circuit having an input receiving a digital inputdata having n bits for selecting one of a plurality of voltage levelsfor driving the circuit. The circuit also has an output, a plurality ofdigital signal lines coupled to the digital input data, and a pluralityof active regions coupled to a first side of the output. Each of theplurality of active regions is coupled to a separate voltage level. Thecircuit further includes a plurality of pass transistors at a firstsubset of locations where the plurality of digital signal lines overlapthe plurality of active regions, and a plurality of depletion-implantedtransistors at a second subset of locations where the plurality ofdigital signal lines overlap the plurality of active regions. It is alsopossible to provide a second plurality of active regions coupled to asecond side of the output.

[0017] In one embodiment of the present invention, the number of theplurality of digital signal lines on one side of the output is an oddnumber, and can be 2n−1.

[0018] In another embodiment of the present invention, the number of theplurality of digital signal lines on one side of the output can be 2n−2.

[0019] In yet another embodiment of the present invention, a pluralityof blocking transistors are positioned between the input and selecteddigital signal lines, with at least one of the digital signal linesbeing coupled to a gate of each of the blocking transistors forcontrolling each of the blocking transistors.

[0020] In yet another embodiment of the present invention, alevel-shifter can be positioned between selected active regions for oneor more digital signal line.

[0021] The improvements set forth in these embodiments are directedprimarily to conserving power and layout space.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The invention can be more fully understood by reading thesubsequent detailed description of the preferred embodiments, withreference made to the accompanying drawings.

[0023]FIG. 1 illustrates a conventional LCD driver circuit.

[0024]FIG. 2 illustrates a signal-line routing scheme based on theconventional LCD driver in FIG. 1.

[0025]FIG. 3 illustrates a LCD driver circuit and routing scheme for acommercial LCD driver.

[0026]FIG. 4 is a top view of the layout of FIG. 3.

[0027]FIG. 5 is a top view of a layout for a driver circuit according toone embodiment of the present invention.

[0028]FIG. 6 is a top view of a layout for a driver circuit according toanother embodiment of the present invention.

[0029]FIG. 7 is a top view of a layout for a driver circuit according toyet another embodiment of the present invention.

[0030]FIGS. 8a, 8 b, 9 a and 9 b illustrate different inverting gatesthat can be used with the circuit of FIG. 7.

[0031]FIG. 10 is a top view of a layout for a driver circuit accordingto yet another embodiment of the present invention.

[0032]FIG. 11 illustrates an LCD driver according to another embodimentof the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0033] In the following description, for purposes of explanation and notlimitation, specific details are set forth in order to provide athorough understanding of the present invention. However, it will beapparent to one skilled in the art that the present invention may bepracticed in other embodiments that depart from these specific details.In certain instances, detailed descriptions of well-known orconventional data processing techniques, hardware devices and circuitsare omitted so as to not obscure the description of the presentinvention with unnecessary detail.

[0034] The present invention provides a number of improvements toconventional LCD driver circuits and routing schemes, such as those forthe commercial LCD driver of FIGS. 3 and 4. Even though the embodimentsof the present invention will be illustrated using the basic circuits,layout and routing scheme shown in FIGS. 3 and 4, this is not intendedto limit the scope of the principles of the present invention, which canbe applied to numerous other circuits, layouts and routing schemes. Eachof the improvements set forth in the present invention in FIGS. 5-10 canbe implemented alone, or combined with one or more of the otherimprovements. The improvements set forth herein are directed primarilyto conserving power and layout space, although other objectives willbecome apparent to those skilled in the art.

[0035] First Embodiment

[0036]FIG. 5 illustrates a first possible improvement, which attempts toreduce the number of signal lines, thereby conserving space in thelayout. This embodiment is based on the principle of utilizing a firstdigital signal to select or decode half of the analog voltage lines, andthe use of the inverted first digital signal to select or decode theother half of the analog voltage lines, while using the combination ofthe other digital signals to select one from the selected half of theanalog voltage lines. As used herein, the term “voltage line” is used todenote the line on which a voltage level is being delivered.

[0037] The layout 100 in FIG. 5 is essentially the same as in FIG. 4,except that the signal line {c} has been omitted or eliminated for theeven-numbered voltage levels {V0, V2, V4, V6} on one side, and thesignal line {c-bar} has been omitted or eliminated for the odd-numberedvoltage levels {V1, V3, V5, V7} on the other side. The signal line {c}can be eliminated for the even-numbered voltage levels {V0, V2, V4, V6}because depletion implanted transistors are provided at all the overlapsbetween the even-numbered voltage levels {V0, V2, V4, V6} and the signalline {c}. Similarly, the signal line {c-bar} can be eliminated for theodd-numbered voltage levels {V1, V3, V5, V7} because depletion implantedtransistors are provided at all the overlaps between the odd-numberedvoltage levels {V1, V3, V5, V7} and the signal line {c-bar}. In otherwords, the signal line {c} is useless for the selection of even-numberedvoltage levels {V0, V2, V4, V6}, and the signal line {c-bar} is uselessfor the selection of odd-numbered voltage levels {V1, V3, V5, V7}. Thisimprovement can be achieved because each of the signal lines {c} and{c-bar} crosses only half of the eight active regions AR.

[0038] Even though FIG. 5 illustrates the elimination of the signallines {c} (for the upper side of FIG. 5) and {c-bar} (for the lower sideof FIG. 5), this is for illustrative purposes only and is based on thespecific layout shown in FIG. 5. Depending on the layout selected by thecircuit designer, any one or more of the other digital signal lines {a,a-bar, b, b-bar, c, c-bar} can be eliminated if the same conditions aremet (e.g., depletion implanted transistors at all the overlaps).

[0039] Thus, the layout 100 in FIG. 5 eliminates one signal line oneither side of the output, so that only a total of 2n−1 lines are nowneeded on each side. This reduction in signal lines helps to conservespace and minimizes the power consumption of the driver circuit.

[0040] Second Embodiment

[0041]FIG. 6 illustrates another possible improvement, which attempts toblock a subset of the digital signals from propagating to certain passtransistors, thereby conserving power. In this regard, it is well-knownthat when CMOS gates are used, power consumption results whenever a CMOSgate changes its logic level. Therefore, this embodiment is based on theprinciple of anticipating the circumstances under which certain passtransistors will not be needed, and then blocking the transmission ofdigital signals to these pass transistors so that these pass transistorswill not need to experience a change in logic level. In other words, oneor more digital signal lines are blocked based on the logic state of oneor more other digital signal lines.

[0042] The layout 200 in FIG. 6 is essentially the same as in FIG. 5,except that additional pass transistors M0, M1, M2, M3, M4, M5, M6, M7(referred to hereinafter as “blocking transistors”) have been providedto block certain digital signals from propagating to the digital linedecoding area. The digital line decoding area is defined as the areaformed by the overlapping digital lines and active regions AR associatedwith analog voltage levels. In FIG. 6, it can be seen that when thesignal {c-bar} is logic “low” (i.e., signal {c} is logic “high”), noneof the even-numbered voltage levels {V0, V2, V4, V6} on one side of FIG.6 will be selected as the output. As a result, if {c-bar} is logic“low”, it would be a waste of power to have the digital signals {a,a-bar, b, b-bar} still propagate to the pass transistors PT associatedwith the even-numbered voltage levels {V0, V2, V4, V6} in the upper sideof FIG. 6, since these pass transistors will still change logic levels(and consume power) even though they will be not be able to select anyof these even-numbered voltage levels {V0, V2, V4, V6}. Thus, blockingtransistors M0, M1, M2, M3 are provided at the inputs of the digitalsignals {a, a-bar, b, b-bar}, respectively, on one side of FIG. 6 toblock these digital signals from propagating into the digital linedecoding area if the signal {c-bar} is logic “low”.

[0043] Similarly, it can be seen that when the signal {c} is logic“low”, none of the odd-numbered voltage levels {V1, V3, V5, V7} on theother side of FIG. 6 will be selected as the output. Thus, blockingtransistors M4, M5, M6, M7 are provided at the inputs of the digitalsignals {b-bar, b, a-bar, a}, respectively, on the other side of FIG. 6to block these digital signals from propagating into the digital linedecoding area if the signal {c} is logic “low”. The blocking transistors{M0, . . . , M7} can be provided in the form of NMOS switching gates.

[0044] In addition, signal-driving buffers 210 can be coupled to theblocking transistors {M0, . . . , M7} at the digital signal inputs toamplify each digital signal {a, a-bar, b, b-bar, c, c-bar} before theyare used to drive the pass transistors PT. Since the {c} and {c-bar}signals must change faster than the other digital signals {a, a-bar, b,b-bar} in order to cause the blocking transistors {M0, . . . , M7} toturn on more quickly (for blocking selected digital signals), largerbuffers 210 a can be used to drive the signals c and c-bar than theother buffers 210. These buffers 210, 210 a can be provided in the formof an inverter, as shown in FIG. 6, although any other conventionalsignal driving buffer can also be utilized.

[0045] As another alternative, CMOS transfer gates may be used insteadof the blocking transistors {M0, . . . , M7} to preserve the full logicswing of the digital signals {a, a-bar, b, b-bar} when these digitalsignals pass therethrough.

[0046] Even though FIG. 6 illustrates the provision of the blockingtransistors {M0, M7} together with the principle of reducing the numberof digital lines as shown in FIG. 5, it is also possible to apply theprinciples of FIG. 6 independently without the reduction of signallines. In addition, even though FIG. 6 illustrates the use of the signallines {c} and {c-bar} to control the blocking transistors {M0, . . . ,M7}, this is for illustrative purposes only and is based on the specificlayout shown in FIG. 6. Depending on the layout selected by the circuitdesigner, any one or more of the six digital signal lines {a, a-bar, b,b-bar, c, c-bar} can be used for controlling the blocking transistors{M0, . . . , M7}.

[0047] Third Embodiment

[0048]FIG. 7 illustrates another possible improvement, which attempts tofurther reduce the number of digital signal lines. This embodiment isalso based on the same principles of FIG. 5, but also including theprinciple of using a digital signal for selecting or decoding one rangeof voltage levels, and an inverter associated with the digital signalfor selecting or decoding a different range of voltage levels. In otherwords, this embodiment utilizes (explained in greater detail below):

[0049] 1. a first signal poly line (e.g., {c}) for selecting/decoding afirst subset of voltage levels (e.g., V1, V3, V5, V7);

[0050] 2. an inverted first signal poly line (e.g., {c-bar}) forselecting/decoding a second subset (complementary to the first subset)of voltage levels (e.g., V0, V2, V4, V6);

[0051] 3. a second signal poly line (e.g., {a-bar}) forselecting/decoding a third subset of voltage levels (e.g., V0, V1, V2,V3) partly from the first subset, and partly from the second subset, ofvoltage levels; and

[0052] 4. an inverted second signal poly line (e.g., {a′} and {a″}) forselecting/decoding a fourth subset (complementary to the third subset)of voltage levels (e.g., V4, V5, V6, V7) partly from the first subset,and partly from the second subset, of voltage levels.

[0053] The layout 300 in FIG. 7 is essentially the same as in FIG. 6,except that the signal lines {a} and {a-bar} each goes only half-way,and so both share one poly line pitch. Referring back to FIG. 4, it canbe seen that a logic “high” for the signal {abar} selects one of thevoltage levels {V0, V1, V2, V3}, and that a logic “high” for the signal{a} selects one of the voltage levels {V4, V5, V6, V7}. Based on thischaracteristic, the pitch for the original signal line {a} can beeliminated, and inverting gates X1 and X2 (which in one embodiment canbe CMOS gates) can be positioned on the signal lines {a-bar} between theactive regions for voltage levels V2 and V4, and between the activeregions voltage levels V3 and V5, respectively. This positioning of theinverting gates X1 and X2 allows the signal {a-bar} to only propagate tothe active regions for the lower voltage levels {V0, V1, V2, V3}. Theinverting gates X1 and X2 will invert the {a-bar} signal to the signals{a′} and {a″} (which are actually the same as the signal {a}) which thenpropogate to the active regions for the upper voltage levels {V4, V5,V6, V7}.

[0054] If the input of the inverting gate X1 turns into an undesirablefloating state after the signal line {a-bar} is cut off by the blockingtransistor M2, it can cause excess power consumption for the invertinggate X1. For example, if the inverting gate X1 is a CMOS inverter, andif the input voltage at the gate X1 is not at “high” or “low”, then boththe pull-up PMOS and pull-down NMOS are partly turned on. This resultsin a “crowbar” current that goes straight from VDD to VSS causing powerloss. To avoid this problem, the inverting gate X1 can be configured asshown in FIG. 8a or 9 a, such that when the signal {c-bar} is at logic“low”, no crowbar current can flow directly from VDD to VSS as a resultof a floating input (i.e., {a-bar}) of inverting gate X1.

[0055] Referring to FIG. 8a, since the input to gate X1 is floating onlywhen the signal {c-bar} is at “low”, by using {c-bar} to cut off N2 inthe gate X1 when {c-bar} is at “low”, the current path from VDD to VSSin gate X1 will be blocked, so that there will be no “crowbar” currenteven if the input to gate X1 is floating. The signal {a′} might befloating or pulled high by the partially turned on P1, but this will notcause much power consumption. Similarly, in the embodiment of FIG. 9a,when the signal {c-bar} is at “low” and the signal {c} is at “high”,both N2 and P2 are cut off, so that there will be no “crowbar” currenteven if the input to gate X1 is floating, and the signal {a′} line willnot be charged by VDD.

[0056] Similarly, the inverting gate X2 can be configured as shown inFIG. 8b or 9 b, such that when the signal {c} is at logic “low”, nocrowbar current can flow directly from VDD to VSS as a result of afloating input (i.e., {a-bar}) of inverting gate X2. The gates X2 shownin FIGS. 8b and 9 b are symmetrical to those shown in FIGS. 8a and 9 a,and operate in a similar manner.

[0057] As with FIG. 6, CMOS transfer gates may be used instead of theblocking transistors {M0, . . . , M7} to preserve the full logic swingof the digital signals {a-bar, b, b-bar} when these digital signals passtherethrough. However, in FIG. 7, the blocking transistors M2 and M6(for the {a-bar} digital signal lines) can remain as NMOS switchinggates since the signal {a-bar} is only used to pass the lower voltagerange of {V0, V1, V2, V3} and it is not necessary to have full logicswing. The signal {a} is after the CMOS buffer X1, so the full voltageswing of signal {a} is helpful for passing the higher voltage range {V4,V5, V6, V7}.

[0058] Thus, the layout 300 in FIG. 7 eliminates another signal line oneither side of the output, so that only a total of 2n−2 signal lines arenow needed on each side of the output or layout. This reduction insignal lines further helps to conserve space and minimizes the powerconsumption of the driver circuit. These savings can be significant. Forexample, if n=3, the savings in digital-line pitch is 33%.

[0059] Even though FIG. 7 illustrates the elimination of the signallines {a} together with the principles illustrated in connection withFIGS. 5 and 6, it is also possible to apply the principles of FIG. 7independently without the principles of FIGS. 5 and 6, or in combinationwith the principles of FIG. 5 only or FIG. 6 only. In addition, eventhough FIG. 7 illustrates the elimination of the signal lines {a}, thisis for illustrative purposes only and is based on the specific layoutshown in FIG. 7. Depending on the layout selected by the circuitdesigner, any of the other digital signal lines {a-bar, b, b-bar, c,c-bar} can be eliminated.

[0060] Fourth Embodiment

[0061]FIG. 10 illustrates another possible improvement, which is relatedto level-shifting a portion of a digital signal line, so as to achievesignificant power conservation without affecting theanalog-voltage-selection functionality. In this regard, it is well-knownthat when power consumption P is equal to:

P=fcv ²

[0062] where f is the switching frequency, c is the capacitance, and vis equal to (VH−VL), where VH represents the high voltage level, and VLrepresents the low voltage level. For example, for a 5V signal, VHNL is5V/0V, and for a 10V signal, VH/VL is 10V/0V. In other words, the powerP is proportional to (VH−VL)². Therefore, cutting the voltage swing byhalf means that power consumption can be reduced to ¼.

[0063] The layout 400 in FIG. 10 is essentially the same as in FIG. 7,except that a level-shifter {L1, L2, L3, L4, L5, L6, L7, L8} has beenpositioned along each digital signal line between the active regions forvoltage levels V2 and V4, and between the active regions for voltagelevels V3 and V5. The level-shifter can be coupled between two segmentsof a digital signal line, which might be discontinued between selectedactive regions to form the two discontinued segments. Further, thelevel-shifter can be positioned between the active regions for twoadjacent voltage levels (e.g., positioned on an actual digital signalbetween the active regions for two adjacent voltage levels).

[0064] As an example, assume that the LCD circuit of FIG. 10 has a full10-volt range. Since VH-VL is equal to 10 volts, the power required todrive the circuit can be quite high. However, if the voltage levels for{V0, V1, V2, V3} are set at a range of 0-5 volts, for example, and thevoltage levels for {V4, V5, V6, V7} are set at a range of 5-10 volts,for example, then much less power is required to drive the circuitbecause VH−VL would be equal to 5 volts for all voltage levels {V0, V1,V2, V3, V4, V5, V6, V7}. The circuit in FIG. 10 accomplishes this bypositioning a level-shifter {L1, L2, L3, L4, L5, L6, L7, L8} on ordividing each digital signal line between the active regions for voltagelevels V2 and V4, and between the active regions for voltage levels V3and V5. Level-shifters L4 and L8 could be coupled to the outputs of theinverting gates X1 and X2, respectively. Each level-shifter {L1, L2, L3,L4, L5, L6, L7, L8} can be implemented in any form that is well-known inthe art.

[0065] In a preferred embodiment of the present invention, significantpower savings can be achieved by using a 0 to 6 volt range for thedigital signals {a, a-bar, b, b-bar, c, c-bar} that are used to selectthe lower-range voltage levels {V0, V1, V2, V3}, and using a 4 to 10volt range for the digital signals {a, a-bar, b, b-bar, c, c-bar} forselecting the upper-range voltage levels {V4, V5, V6, V7}. Thelevel-shifters {L1, L2, L3, L4, L5, L6, L7, L8} function to shift thevoltage range of the digital signals from the 0-6 volt range to the 4-10volt range. Using the 0-6 volt and 4-10 volt ranges, the powerconsumption can be reduced by (6/10)²=36%, for a 64% power savings.

[0066] The concept of level-shifting can also be applied to the circuitof FIG. 1. FIG. 11 illustrates the provision of level-shifters L11 andL21 in the LCD circuit of FIG. 1 to level-shift a subset of digitalsignals for selecting a subset of voltage levels (here, V3 and V2,respectively).

[0067] Even though FIG. 10 illustrates the use of level-shifterstogether with the principles illustrated in connection with FIGS. 5, 6and 7, it is also possible to apply the principles of FIG. 10independently without the principles of FIGS. 5, 6, and 7 or incombination with the principles of one or more of FIGS. 5, 6 and 7.

[0068] It will be recognized that the above described invention may beembodied in other specific forms without departing from the spirit oressential characteristics of the disclosure. Thus, it is understood thatthe invention is not to be limited by the foregoing illustrativedetails, but rather is to be defined by the appended claims. As onenon-limiting example, even though FIGS. 5-7 and 10 have been illustratedas using six digital signal lines {a, a-bar, b, b-bar, c, c-bar} andeight voltage levels {V0, . . . V7}, it is possible to use any number ofdigital signal lines and voltage levels (e.g., 2n−x digital signal linesfor 2^(n) voltage levels). As another non-limiting example, theprinciples of the present invention can be applied to general DACs(digital-to-analog converters) with digital decoders and analog voltageoutputs.

What is claimed is:
 1. A driver circuit for a display, the circuit having an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit, the circuit having an output, a plurality of digital signal lines coupled to the digital input data, a plurality of active regions coupled to a first side of the output, each of the plurality of active regions coupled to a separate voltage level, the circuit further including a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions, wherein: the number of the plurality of digital signal lines on the first side of the output is an odd number.
 2. The circuit of claim 1, wherein the plurality of digital signal lines are polysilicon lines.
 3. The circuit of claim 1, wherein the plurality of active regions is a first plurality of active regions, and further including a second plurality of active regions coupled to a second side of the output, and the number of the plurality of digital signal lines on the second side of the output is an odd number.
 4. The circuit of claim 1, wherein the number of the plurality of digital signal lines on the first side of the output is equal to 2n−1.
 5. The circuit of claim 3, wherein the number of the plurality of digital signal lines on the second side of the output is equal to 2n−1.
 6. The circuit of claim 1, wherein said odd number digital signal lines includes a first digital signal line associated with a first digital bit, a second digital signal associated with a second digital bit, and an inverting digital line associated with the second digital bit.
 7. A driver circuit for a display, the circuit having an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit, the circuit having an output, a plurality of digital signal lines coupled to the digital input data, a plurality of active regions coupled to a first side of the output, each of the plurality of active regions coupled to a separate voltage level, the circuit further including a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions, the circuit further including: a plurality of blocking transistors positioned between the input and selected digital signal lines, with at least one of the digital signal lines being coupled to a gate of each of the blocking transistors for controlling each of the blocking transistors.
 8. The circuit of claim 7, wherein the plurality of active regions is a first plurality of active regions, and further including a second plurality of active regions coupled to a second side of the output, and the number of the plurality of digital signal lines on the second side of the output is an odd number.
 9. The circuit of claim 7, further including a buffer positioned between the input and each digital signal line, wherein the buffers for the digital signal lines that control the blocking transistors are larger in size than the other buffers.
 10. The circuit of claim 7, wherein each blocking transistor is either a NMOS switching gate or a CMOS transfer gate.
 11. The circuit of claim 7, wherein the number of the plurality of digital signal lines on the first side of the output is an odd number.
 12. The circuit of claim 8, wherein the number of the plurality of digital signal lines on the second side of the output is equal to 2n−1.
 13. The circuit of claim 11, wherein the number of the plurality of digital signal lines on the first side of the output is equal to 2n−1.
 14. A driver circuit for a display, the circuit having an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit, the circuit having an output, a plurality of digital signal lines coupled to the digital input data, a plurality of active regions coupled to a first side of the output, each of the plurality of active regions coupled to a separate voltage level, the circuit further including a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions, wherein: the number of the plurality of digital signal lines on the first side of the output is equal to 2n−2.
 15. The circuit of claim 14, wherein the plurality of digital signal lines are polysilicon lines.
 16. The circuit of claim 14, wherein the plurality of active regions is a first plurality of active regions, and further including a second plurality of active regions coupled to a second side of the output, and the number of the plurality of digital signal lines on the second side of the output is equal to 2n−2.
 17. The circuit of claim 14, wherein a first of the digital signal lines is discontinued between two adjacent active regions to form a first digital segment carrying the digital signal, and a second digital segment carrying a digital signal that is inverted from the digital signal of the first digital segment.
 18. The circuit of claim 16, wherein one of the digital signal lines on the second side is discontinued between two adjacent active regions to form a first digital segment carrying the digital signal, and a second digital segment carrying a digital signal that is inverted from the digital signal of the first digital segment.
 19. The circuit of claim 14, further including a plurality of blocking transistors positioned between the input and selected digital signal lines, with at least one of the digital signal lines being coupled to a gate of each of the blocking
 27. The circuit of claim 21, wherein a first of the digital signal lines is discontinued between two adjacent active regions to form a first digital segment carrying the digital signal, and a second digital segment carrying a digital signal that is inverted from the digital signal of the first digital segment.
 28. The circuit of claim 21, wherein the plurality of active regions is a first plurality of active regions, and further including a second plurality of active regions coupled to a second side of the output.
 29. The circuit of claim 28, wherein the number of the plurality of digital signal lines on the second side of the output is equal to 2n−2.
 30. The circuit of claim 28, wherein the number of the plurality of digital signal lines on the second side of the output is equal to 2n−1.
 31. The circuit of claim 28, wherein one of the digital signal lines on the second side is discontinued between two adjacent active regions to form a first digital segment carrying the digital signal, and a second digital segment carrying a digital signal that is inverted from the digital signal of the first digital segment.
 32. The circuit of claim 21, wherein the digital signal line has at least two discontinued segments, with a level shifter coupling between the the discontinued segments. 